Abstract—The modern microprocessor architecture mainly utilizes multi-level data caches as a primary optimization to reduce the memory access latency and power consumption as well as increase the perceived bandwidth from an application. This mechanism works well with significant memory reuse or linear memory access patterns. However, the irregular or nondeterministic pattern of memory access will result in a high miss rate in both cache and Transaction Look-aside Buffer (TLB), which subsequently leads to high memory access latency and power consumptions. In response to these data-intensive applications, Leidel et al. developed the GoblinCore-64(GC64) microarchitecture by using a large degree of hardware-managed concurrency coupled to a high bandwidth memory subsystem. Wang et al. proposed the Concurrent Dynamic Memory Coalescing within the GC64 architecture explicitly designed to exploit memory performance from irregular memory access patterns. In this research, we will investigate the memory power consumption savings to evaluate the efficacy of the aforementioned works.